1. Field of the Invention
The present invention relates to a capacitor for a semiconductor device and a manufacturing method thereof, and more particularly, to a two-mask process for manufacturing a capacitor having a metal-insulator-metal structure.
2. Description of Related Art
Capacitors in semiconductor devices are often integrated with active bipolar or MOS transistors for analog and digital circuits. Capacitors of various types have been used in the art, such as polysilicon-insulator-polysilicon (PIP) capacitors, polysilicon-insulator-polycide capacitors, polysilicon-insulator-metal (MIS) capacitors, and metal-insulator-metal (MIM) capacitors. Capacitors in semiconductors are required to maintain large capacitance values even though integration requires capacitor area to continue to decrease. To accommodate, capacitors are being formed near and over transistors, for example at the metal level as opposed to being formed at the transistor level nearer the bulk semiconductor substrate. A MIM capacitor is one such example for accommodating a larger capacitor in a smaller size.
MIM capacitors are planar structures consisting of a thin dielectric sandwiched between two metallic electrodes. MIM capacitors are essential components in radio frequency (RF) analog applications and in mixed digital-analog circuits. The prior art process of record for MIM capacitor fabrication requires at least three lithographic mask levels to add a MIM capacitor onto an otherwise standard interconnect structure. Such processes of record have been utilized in generations of CMOS and RF applications. A three phase lithographic process is an expensive process in cost sensitive markets such as RF communications and ASICs. The need for three lithographic levels arises from the fact that metallic electrodes used in current MIM capacitor technologies are opaque to optical light, and thus prevent the lithography tools from aligning to the previous copper interconnect layer. A process that decreases lithographic steps would reduce complexity and realize a significant cost savings in the MIM capacitor module build. Moreover, in addition to reducing cost, a direct alignment scheme would be more accurate than the current trench alignment scheme of the prior art. In the prior art, trenches are patterned and etched in an oxide layer to form alignment marks for further process steps. A more robust alignment process would also reduce lithographic rework. Further, the reduced mask process may be adaptable to thin film resistor fabrication with similar benefits realized.
FIG. 1 depicts the typical MIM capacitor process flow of the prior art. As shown in FIG. 1A, a silicon oxide (SiO2) layer 12, that is generally used for alignment purposes, is deposited on a semiconductor substrate's nitride layer 10. A first mask or photoresist 14 is applied to pattern the trenches or alignment marks 16. As shown in FIG. 1B, alignment marks 16 are reactive ion etched, and the photoresist removed. FIG. 1C depicts layers of titanium nitride TiNx 18 and silicon nitride SiNx 20 that are then deposited on the structure. In FIG. 1C, a second mask or photoresist 22 is used to pattern the MIM capacitor's top electrode. FIG. 1D shows the patterned structure again subjected to a reactive ion etch with the photoresist 22 subsequently removed. In FIG. 1E, a third mask 24 is applied to pattern a bottom electrode. FIG. 1F depicts the structure of FIG. 1E after reactive ion etching. An oxide interlayer dielectric 26 is deposited on the structure of FIG. 1F, and planarized as shown in FIG. 1G. FIG. 1H shows the structure after lines and/or vias 28 are patterned and etched. A metal liner and metal fill 30 are then added to the lines and/or vias 28, and subjected to a chemical-mechanical polish (CMP), as shown in FIG. 1I. The prior art requires this three-mask process due, in part, to the necessity of fabricating a trenched layer of SiO2 for alignment purposes.
In U.S. Pat. No. 6,413,815 issued to Lai et al., on Jul. 2, 2002, entitled, “METHOD OF FORMING A MIM CAPACITOR,” three photoresists are used to form a MIM capacitor, as is the general method practiced by the prior art. The first photoresist forms trenches in a dielectric layer for alignment purposes. The second photoresist forms the top electrode of the MIM capacitor, and the third photoresist forms the bottom electrode of the MIM capacitor. The Lai design and other designs in the prior art do not teach or disclose eliminating the formation of alignment trenches by a first photoresist application as does the present invention.
The TiNx films currently used in MIM capacitor processes are opaque to the transmission of visible light. Further, due to the highly planar copper surface below the MIM capacitor, the TiNx layer acts as a specularly reflective mirror preventing the proper alignment and overlay measurements. To overcome these problems, the prior art process of record requires the introduction of topography, such as trenches and the like, into the reflecting surface. This topography is achieved by using an extra masking level, followed by a reactive ion etch step. A TiNx/SiNx film stack conformally covers the resulting alignment marks, which are typically 350 Angstroms deep in the sacrificial oxide film. The 350 Angstrom topography in the otherwise mirror-like structure leads to non-specular reflected light, which allows for alignment and overlay to the copper level below. The elimination of this mask step and trench formation is a significant advancement over the current prior art.
FIG. 2 depicts the two-mask prior art process for fabricating thin film resistors. First, as shown in FIG. 2A, a layer of SiO2 204 is deposited on the nitride layer 202 of a substrate 200 and patterned with a first photoresist mask 206. The mask is designed to allow trenches to be etched within the SiO2 layer. FIG. 2B depicts the SiO2 layer 204 with trenches 208 present after a reactive ion etch. Next, as shown in FIG. 2C, resistor material 210, such as TiNx is deposited and patterned with a second photoresist mask 212, aligned to the trench marks 208 of the previous process step. The substrate is subjected to a second reactive ion etch, and the photoresist 212 is then stripped. The resultant patterned structure is depicted in FIG. 2D. The patterned resistor material 210 is shown for the desired resistor structure. Notably, two masks are used in this prior art process to fabricate the thin film resistor.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a process for fabricating MIM capacitors that decreases the lithographic steps.
It is another object of the present invention to provide a process for fabricating MIM capacitors that allows for a more accurate direct alignment scheme than the current trench alignment scheme.
A further object of the invention is to provide a process for fabricating MIM capacitors that allows for lithography tools to align to a previous copper interconnect layer without the need for trench alignment marks.
It is another object of the present invention is to eliminate the need to create topography for decreasing reflectivity within device structure.
It is yet another object of the present invention to provide a reduced mask process for application to a thin film resistor.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.